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1 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b 32m-bit [4m x 8 / 2m x 16] single voltage 3v only flash memory features general features ? 4,194,304 x 8 / 2,097,152 x 16 switchable sector structure - 8k-byte x 8 and 64k-byte x 63 extra 64k-byte sector for security - features factory locked and identifiable, and cus- tomer lockable twenty-four sector groups - provides sector group protect function to prevent pro- gram or erase operation in the protected sector group - provides chip unprotect function to allow code chang- ing - provides temporary sector group unprotect function for code changing in previously protected sector groups single power supply operation - 2.7 to 3.6 volt for read, erase, and program opera- tions latch-up protected to 250ma from -1v to vcc + 1v low vcc write inhibit is equal to or less than 1.4v compatible with jedec standard - pinout and software compatible to single power sup- ply flash fully compatible with kh29lv320a t/b device performance high performance - fast access time: 70/90ns - fast program time: 7us/word typical utilizing acceler- ate function - fast erase time: 0.9s/sector, 35s/chip (typical) low power consumption - low active read current: 10ma (typical) at 5mhz - low standby current: 200na (typical) minimum 100,000 erase/program cycle 10 years data retention software features erase suspend/ erase resume - suspends sector erase operation to read data from or program data to another sector which is not being erased status reply - data# polling & toggle bits provide detection of pro- gram and erase operation completion support common flash interface (cfi) hardware features ready/busy# (ry/by#) output - provides a hardware method of detecting program and erase operation completion hardware reset (reset#) input - provides a hardware method to reset the internal state machine to read mode wp#/acc input pin - provides accelerated program capability package 48-pin tsop all pb-free devices are rohs compliant general description the kh29lv320c t/b is a 32-mega bit flash memory organized as 4m bytes of 8 bits and 2m words of 16 bits. mxic's flash memories offer the most cost-effective and reliable read/write non-volatile random access memory. the kh29lv320c t/b is packaged in 48-pin tsop. it is designed to be reprogrammed and erased in system or in standard eprom programmers. the standard kh29lv320c t/b offers access time as fast as 70ns, allowing operation of high-speed micropro- cessors without wait states. to eliminate bus conten- tion, the kh29lv320c t/b has separate chip enable (ce#) and output enable (oe#) controls. mxic's flash memories augment eprom functionality with in-circuit electrical erasure and programming. the kh29lv320c t/b uses a command register to manage this functionality. mxic flash technology reliably stores memory contents even after 100,000 erase and program cycles. the mxic cell is designed to optimize the erase and program mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable
2 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b cycling. the kh29lv320c t/b uses a 2.7v to 3.6v vcc supply to perform the high reliability erase and auto program/erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up protection is proved for stresses up to 100 milliamperes on address and data pin from -1v to vcc + 1v. automatic programming the kh29lv320c t/b is byte/word programmable using the automatic programming algorithm. the automatic programming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. the typical chip programming time at room temperature of the kh29lv320c t/b is less than 36 seconds. automatic programming algorithm mxic's automatic programming algorithm require the user to only write program set-up commands (including 2 un- lock write cycle and a0h) and a program command (pro- gram data and address). the device automatically times the programming pulse width, provides the program veri- fication, and counts the number of sequences. a status bit similar to data# polling and a status bit toggling be- tween consecutive read cycles, provide feedback to the user as to the status of the programming operation. automatic chip erase the entire chip is bulk erased using 50 ms erase pulses according to mxic's automatic chip erase algorithm. typical erasure at room temperature is accomplished in less than 35 seconds. the automatic erase algorithm automatically programs the entire array prior to electrical erase. the timing and verification of electrical erase are controlled internally within the device. automatic sector erase the kh29lv320c t/b is sector(s) erasable using mxic's auto sector erase algorithm. sector erase modes allow sectors of the array to be erased in one erase cycle. the automatic sector erase algorithm automatically programs the specified sector(s) prior to electrical erase. the timing and verification of electri- cal erase are controlled internally within the device. automatic erase algorithm mxic's automatic erase algorithm requires the user to write commands to the command register using stand- ard microprocessor write timings. the device will auto- matically pre-program and verify the entire array. then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. a status bit toggling between consecutive read cycles provides feedback to the user as to the sta- tus of the programming operation. register contents serve as inputs to an internal state- machine which controls the erase and programming cir- cuitry. during write cycles, the command register inter- nally latches address and data needed for the program- ming and erase operations. during a system write cycle, addresses are latched on the falling edge, and data are latched on the rising edge of we# . mxic's flash technology combines years of eprom experience to produce the highest levels of quality, relia- bility, and cost effectiveness. the kh29lv320c t/b elec- trically erases all bits simultaneously using fowler-nord- heim tunneling. the bytes/words are programmed by using the eprom programming mechanism of hot elec- tron injection. during a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. during a sector erase cycle, the command register will only respond to erase suspend command. after erase suspend is completed, the device stays in read mode. after the state machine has completed its task, it will allow the command regis- ter to respond to its full command set.
3 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b pin configuration 48 tsop symbol pin name a0~a20 address input q0~q14 15 data inputs/outputs q15/a-1 q15(data input/output, word mode) a-1(lsb address input, byte mode) ce# chip enable input we# write enable input oe# output enable input byte# word/byte selection input reset# hardware reset pin, active low ry/by# read/busy output vcc 3.0 volt-only single power supply wp#/acc hardw are write protect/acceleration pin gnd device ground nc pin not connected internally pin description logic symbol 16 or 8 q0-q15 (a-1) ry/by# a0-a20 ce# oe# we# reset# wp#/acc byte# 21 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# nc wp#/acc ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 byte# gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 vcc q11 q3 q10 q2 q9 q1 q8 q0 oe# gnd ce# a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 kh29lv320c t/b
4 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15/a-1 a0-a20 ce# oe# we# reset# byte#
5 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b sector sector sector address sector size (x8) (x16) group a20-a12 (kbytes/kwords) address range address range 1 sa0 000000xxx 64/32 000000h-00ffffh 000000h-07fffh 1 sa1 000001xxx 64/32 010000h-01ffffh 008000h-0ffffh 1 sa2 000010xxx 64/32 020000h-02ffffh 010000h-17fffh 1 sa3 000011xxx 64/32 030000h-03ffffh 018000h-01ffffh 2 sa4 000100xxx 64/32 040000h-04ffffh 020000h-027fffh 2 sa5 000101xxx 64/32 050000h-05ffffh 028000h-02ffffh 2 sa6 000110xxx 64/32 060000h-06ffffh 030000h-037fffh 2 sa7 000111xxx 64/32 070000h-07ffffh 038000h-03ffffh 3 sa8 001000xxx 64/32 080000h-08ffffh 040000h-047fffh 3 sa9 001001xxx 64/32 090000h-09ffffh 048000h-04ffffh 3 sa10 001010xxx 64/32 0a0000h-0affffh 050000h-057fffh 3 sa11 001011xxx 64/32 0b0000h-0bffffh 058000h-05ffffh 4 sa12 001100xxx 64/32 0c0000h-0cffffh 060000h-067fffh 4 sa13 001101xxx 64/32 0d0000h-0dffffh 068000h-06ffffh 4 sa14 001110xxx 64/32 0e0000h-0effffh 070000h-077fffh 4 sa15 001111xxx 64/32 0f0000h-0fffffh 078000h-07ffffh 5 sa16 010000xxx 64/32 100000h-10ffffh 080000h-087fffh 5 sa17 010001xxx 64/32 110000h-11ffffh 088000h-08ffffh 5 sa18 010010xxx 64/32 120000h-12ffffh 090000h-097fffh 5 sa19 010011xxx 64/32 130000h-13ffffh 098000h-09ffffh 6 sa20 010100xxx 64/32 140000h-14ffffh 0a0000h-0a7fffh 6 sa21 010101xxx 64/32 150000h-15ffffh 0a8000h-0affffh 6 sa22 010110xxx 64/32 160000h-16ffffh 0b0000h-0b7fffh 6 sa23 010111xxx 64/32 170000h-17ffffh 0b8000h-0bffffh 7 sa24 011000xxx 64/32 180000h-18ffffh 0c0000h-0c7fffh 7 sa25 011001xxx 64/32 190000h-19ffffh 0c8000h-0cffffh 7 sa26 011010xxx 64/32 1a0000h-1affffh 0d0000h-0d7fffh 7 sa27 011011xxx 64/32 1b0000h-1bffffh 0d8000h-0dffffh 8 sa28 011100xxx 64/32 1c0000h-1cffffh 0e0000h-0e7fffh 8 sa29 011101xxx 64/32 1d0000h-1dffffh 0e8000h-0effffh 8 sa30 011110xxx 64/32 1e0000h-1effffh 0f0000h-0f7fffh 8 sa31 011111xxx 64/32 1f0000h-1fffffh 0f8000h-0fffffh 9 sa32 100000xxx 64/32 200000h-20ffffh 100000h-107fffh 9 sa33 100001xxx 64/32 210000h-21ffffh 108000h-10ffffh 9 sa34 100010xxx 64/32 220000h-22ffffh 110000h-117fffh 9 sa35 100011xxx 64/32 230000h-23ffffh 118000h-11ffffh 10 sa36 100100xxx 64/32 240000h-24ffffh 120000h-127fffh 10 sa37 100101xxx 64/32 250000h-25ffffh 128000h-12ffffh 10 sa38 100110xxx 64/32 260000h-26ffffh 130000h-137fffh 10 sa39 100111xxx 64/32 270000h-27ffffh 138000h-13ffffh table 1.a: kh29lv320ct sector group architecture
6 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b sector sector sector address sector size (x8) (x16) group a20-a12 (kbytes/kwords) address range address range 11 sa40 101000xxx 64/32 280000h-28ffffh 140000h-147fffh 11 sa41 101001xxx 64/32 290000h-29ffffh 148000h-14ffffh 11 sa42 101010xxx 64/32 2a0000h-2affffh 150000h-157fffh 11 sa43 101011xxx 64/32 2b0000h-2bffffh 158000h-15ffffh 12 sa44 101100xxx 64/32 2c0000h-2cffffh 160000h-147fffh 12 sa45 101101xxx 64/32 2d0000h-2dffffh 168000h-14ffffh 12 sa46 101110xxx 64/32 2e0000h-2effffh 170000h-177fffh 12 sa47 101111xxx 64/32 2f0000h-2fffffh 178000h-17ffffh 13 sa48 110000xxx 64/32 300000h-30ffffh 180000h-187fffh 13 sa49 110001xxx 64/32 310000h-31ffffh 188000h-18ffffh 13 sa50 110010xxx 64/32 320000h-32ffffh 190000h-197fffh 13 sa51 110011xxx 64/32 330000h-33ffffh 198000h-19ffffh 14 sa52 110100xxx 64/32 340000h-34ffffh 1a0000h-1a7fffh 14 sa53 110101xxx 64/32 350000h-35ffffh 1a8000h-1affffh 14 sa54 110110xxx 64/32 360000h-36ffffh 1b0000h-1b7fffh 14 sa55 110111xxx 64/32 370000h-37ffffh 1b8000h-1bffffh 15 sa56 111000xxx 64/32 380000h-38ffffh 1c0000h-1c7fffh 15 sa57 111001xxx 64/32 390000h-39ffffh 1c8000h-1cffffh 15 sa58 111010xxx 64/32 3a0000h-3affffh 1d0000h-1d7fffh 15 sa59 111011xxx 64/32 3b0000h-3bffffh 1d8000h-1dffffh 16 sa60 111100xxx 64/32 3c0000h-3cffffh 1e0000h-1e7fffh 16 sa61 111101xxx 64/32 3d0000h-3dffffh 1e8000h-1effffh 16 sa62 111110xxx 64/32 3e0000h-3effffh 1f0000h-1f7fffh 17 sa63 111111000 8/4 3f0000h-3f1fffh 1f8000h-1f8fffh 18 sa64 111111001 8/4 3f2000h-3f3fffh 1f9000h-1f9fffh 19 sa65 111111010 8/4 3f4000h-3f5fffh 1f a000h-1fafffh 20 sa66 111111011 8/4 3f6000h-3f7fffh 1fb000h-1fbfffh 21 sa67 111111100 8/4 3f8000h-3f9fffh 1fc000h-1fcfffh 22 sa68 111111101 8/4 3f a000h-3fbfffh 1fd000h-1fdfffh 23 sa69 111111110 8/4 3fc000h-3fdfffh 1fe000h-1fefffh 24 sa70 111111111 8/4 3fe000h-3fffffh 1ff000h-1fffffh top boot security sector addresses sector address sector size (x8) (x16) a20~a12 (kbytes/kwords) address range address range 111111xxx 64/32 3f0000h-3fffffh 1f8000h-1fffffh note:the address range is a20:a-1 in byte mode (byte#=vil) or a20:a0 in word mode (byte#=vih)
7 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b sector sector sector address sector size (x8) (x16) group a20-a12 (kbytes/kwords) address range address range 1 sa0 000000000 8/4 000000h-001fffh 000000h-000fffh 2 sa1 000000001 8/4 002000h-003fffh 001000h-001fffh 3 sa2 000000010 8/4 004000h-005fffh 002000h-002fffh 4 sa3 000000011 8/4 006000h-007fffh 003000h-003fffh 5 sa4 000000100 8/4 008000h-009fffh 004000h-004fffh 6 sa5 000000101 8/4 00a000h-00bfffh 005000h-005fffh 7 sa6 000000110 8/4 00c000h-00dfffh 006000h-006fffh 8 sa7 000000111 8/4 00e000h-00ffffh 007000h-007fffh 9 sa8 000001xxx 64/32 010000h-01ffffh 008000h-00ffffh 9 sa9 000010xxx 64/32 020000h-02ffffh 010000h-017fffh 9 sa10 000011xxx 64/32 030000h-03ffffh 018000h-01ffffh 10 sa11 000100xxx 64/32 040000h-04ffffh 020000h-027fffh 10 sa12 000101xxx 64/32 050000h-05ffffh 028000h-02ffffh 10 sa13 000110xxx 64/32 060000h-06ffffh 030000h-037fffh 10 sa14 000111xxx 64/32 070000h-07ffffh 038000h-03ffffh 11 sa15 001000xxx 64/32 080000h-08ffffh 040000h-047fffh 11 sa16 001001xxx 64/32 090000h-09ffffh 048000h-04ffffh 11 sa17 001010xxx 64/32 0a0000h-0affffh 050000h-057fffh 11 sa18 001011xxx 64/32 0b0000h-0bffffh 058000h-05ffffh 12 sa19 001100xxx 64/32 0c0000h-0cffffh 060000h-067fffh 12 sa20 001101xxx 64/32 0d0000h-0dffffh 068000h-06ffffh 12 sa21 001110xxx 64/32 0e0000h-0effffh 070000h-077fffh 12 sa22 001111xxx 64/32 0f0000h-0fffffh 078000h-07ffffh 13 sa23 010000xxx 64/32 100000h-10ffffh 080000h-087fffh 13 sa24 010001xxx 64/32 110000h-11ffffh 088000h-08ffffh 13 sa25 010010xxx 64/32 120000h-12ffffh 090000h-097fffh 13 sa26 010011xxx 64/32 130000h-13ffffh 098000h-09ffffh 14 sa27 010100xxx 64/32 140000h-14ffffh 0a0000h-0a7fffh 14 sa28 010101xxx 64/32 150000h-15ffffh 0a8000h-0affffh 14 sa29 010110xxx 64/32 160000h-16ffffh 0b0000h-0b7fffh 14 sa30 010111xxx 64/32 170000h-17ffffh 0b8000h-0bffffh 15 sa31 011000xxx 64/32 180000h-18ffffh 0c0000h-0c7fffh 15 sa32 011001xxx 64/32 190000h-19ffffh 0c8000h-0cffffh 15 sa33 011010xxx 64/32 1a0000h-1affffh 0d0000h-0d7fffh 15 sa34 011011xxx 64/32 1b0000h-1bffffh 0d8000h-0dffffh 16 sa35 011100xxx 64/32 1c0000h-1cffffh 0e0000h-0e7fffh 16 sa36 011101xxx 64/32 1d0000h-1dffffh 0e8000h-0effffh 16 sa37 011110xxx 64/32 1e0000h-1effffh 0f0000h-0f7fffh 16 sa38 011111xxx 64/32 1f0000h-1fffffh 0f8000h-0fffffh table 1.b: KH29LV320CB sector group architecture
8 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b sector sector sector address sector size (x8) (x16) group a20-a12 (kbytes/kwords) address range address range 17 sa39 100000xxx 64/32 200000h-20ffffh 100000h-107fffh 17 sa40 100001xxx 64/32 210000h-21ffffh 108000h-10ffffh 17 sa41 100010xxx 64/32 220000h-22ffffh 110000h-117fffh 17 sa42 100011xxx 64/32 230000h-23ffffh 118000h-11ffffh 18 sa43 100100xxx 64/32 240000h-24ffffh 120000h-127fffh 18 sa44 100101xxx 64/32 250000h-25ffffh 128000h-12ffffh 18 sa45 100110xxx 64/32 260000h-26ffffh 130000h-137fffh 18 sa46 100111xxx 64/32 270000h-27ffffh 138000h-13ffffh 19 sa47 101000xxx 64/32 280000h-28ffffh 140000h-147fffh 19 sa48 101001xxx 64/32 290000h-29ffffh 148000h-14ffffh 19 sa49 101010xxx 64/32 2a0000h-2affffh 150000h-157fffh 19 sa50 101011xxx 64/32 2b0000h-2bffffh 158000h-15ffffh 20 sa51 101100xxx 64/32 2c0000h-2cffffh 160000h-167fffh 20 sa52 101101xxx 64/32 2d0000h-2dffffh 168000h-16ffffh 20 sa53 101110xxx 64/32 2e0000h-2effffh 170000h-177fffh 20 sa54 101111xxx 64/32 2f0000h-2fffffh 178000h-17ffffh 21 sa55 110000xxx 64/32 300000h-30ffffh 180000h-187fffh 21 sa56 110001xxx 64/32 310000h-31ffffh 188000h-18ffffh 21 sa57 110010xxx 64/32 320000h-32ffffh 190000h-197fffh 21 sa58 110011xxx 64/32 330000h-33ffffh 198000h-19ffffh 22 sa59 110100xxx 64/32 340000h-34ffffh 1a0000h-1a7fffh 22 sa60 110101xxx 64/32 350000h-35ffffh 1a8000h-1affffh 22 sa61 110110xxx 64/32 360000h-36ffffh 1b0000h-1b7fffh 22 sa62 110111xxx 64/32 370000h-37ffffh 1b8000h-1bffffh 23 sa63 111000xxx 64/32 380000h-38ffffh 1c0000h-1c7fffh 23 sa64 111001xxx 64/32 390000h-39ffffh 1c8000h-1cffffh 23 sa65 111010xxx 64/32 3a0000h-3affffh 1d0000h-1d7fffh 23 sa66 111011xxx 64/32 3b0000h-3bffffh 1d8000h-1dffffh 24 sa67 111100xxx 64/32 3c0000h-3cffffh 1e0000h-1e7fffh 24 sa68 111101xxx 64/32 3d0000h-3dffffh 1e8000h-1effffh 24 sa69 111110xxx 64/32 3e0000h-3effffh 1f0000h-1f7fffh 24 sa70 111111xxx 64/32 3f0000h-3fffffh 1f8000h-1fffffh bottom boot security sector addresses sector address sector size (x8) (x16) a20~a12 (kbytes/kwords) address range address range 111111xxx 64/32 000000h-00ffffh 00000h-07fffh note:the address range is a20:a-1 in byte mode (byte#=vil) or a20:a0 in word mode (byte#=vih)
9 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b operation ce# oe# we# re- wp#/ addresses q0~q7 q8 ~ q15 set# acc (note 2) byte#=vih byte#=vil read l l h h l/h a in d out d out q8-a14 write (note 1) l h l h note 3 a in d in d in =high-z accelerate l h l h v hh a in d in d in q15=a-1 program standby vcc x x vcc h x high-z high-z high-z 0.3v 0.3v output disable l h h h l/h x high-z high-z high-z reset x x x l l/h x high-z high-z high-z sector group l h l vid l/h sector addresses, din, dout x x protect (note 2) a6=l, a1=h, a0=l chip unprotect l h l v id note 3 sector addresses, d in , d out xx (note 2) a6=h, a1=h, a0=l temporary sector x x x v id note 3 a in d in d in high-z group unprotect legend: l=logic low=v il , h=logic high=v ih , v id =12.00.5v, v hh =11.5-12.5v, x=don't care, a in =address in, d in =data in, d out =data out notes: 1. when the wp#/acc pin is at v hh , the device enters the accelerated program mode. see "accelerated program operations" for more information. 2. the sector group protect and chip unprotect functions may also be implemented via programming equipment. see the "sector group protection and chip unprotection" section. 3. if wp#/acc=v il , the two outermost boot sectors remain protected. if wp#/acc=v ih , the two outermost boot sector protection depends on whether they were last protected or unprotected using the method described in "sector/sector block protection and unprotection". if wp#/acc=v hh , all sectors will be unprotected. 4. din or dout as required by command sequence, data polling, or sector protection algorithm. 5. address are a20:a0 in word mode (byte#=v ih ), a20:a-1 in byte mode (byte#=v il ). table 2. bus operation--1
10 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b a20 a11 a8 a5 operation ce# oe# we# to to a9 to a6 to a1 a0 q0-q7 q8-q15 a12 a10 a7 a2 read silicon id l l h x x v id x l x l l c2h x manufacturer code read silicon id l l h x x v id x l x l h a7h 22h(word) kh29lv320ct x (byte) read silicon id l l h x x v id x l x l h a8h 22h(word) KH29LV320CB x (byte) sector protect l l h sa x v id x l x h l 01h(1), x verification or 00h security sector l l h x x v id x l x h h 99h(2), x indicater bit (q7) or 19h bus operation--2 notes: 1.code=00h means unprotected, or code=01h protected. 2.code=99 means factory locked, or code=19h not factory locked.
11 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to vil. ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should re- main at vih. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory con- tent occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the de- vice data outputs. the device remains enabled for read access until the command register contents are altered. write commands/command sequences to program data to the device or erase sectors of memory , the system must drive we# and ce# to vil, and oe# to vih. an erase operation can erase one sector, multiple sec- tors , or the entire device. table 1 indicates the address space that each sector occupies. a "sector address" consists of the address bits required to uniquely select a sector. writing specific address and data commands or sequences into the command register initiates device operations. table 3 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. after the system writes the automatic select command sequence, the device enters the automatic select mode. the system can then read automatic select codes from the internal register (which is separate from the memory array) on q7-q0. standard read cycle timings apply in this mode. refer to the automatic select mode and au- tomatic select command sequence section for more in- formation. icc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the "ac characteristics" section contains timing specification table and timing diagrams for write operations. accelerated program operation the device offers accelerated program operations through the acc function. if the system asserts v hh on wp#/ acc pin, the device will provide the fast programming time to user. this function is primarily intended to allow faster manufacturing throughput during production. re- moving v hh from the wp#/acc pin returns the device to normal operation. note that the wp#/acc pin must not be at v hh for operations other than accelerated program- ming, or device damage may result. standby mode kh29lv320c t/b can be set into standby mode with two different approaches. one is using both ce# and reset# pins and the other one is using reset pin only. when using both pins of ce# and reset#, a cmos standby mode is achieved with both pins held at vcc 0.3v. under this condition, the current consumed is less than 0.2ua (typ.). if both of the ce# and reset# are held at vih, but not within the range of vcc 0.3v, the device will still be in the standby mode, but the standby current will be larger. during auto algorithm operation, vcc active current (icc2) is required even ce# = "h" until the operation is completed. the device can be read with standard access time (tce) from either of these standby modes. when using only reset#, a cmos standby mode is achieved with reset# input held at vss 0.3v, under this condition the current is consumed less than 1ua (typ.). once the reset# pin is taken high, the device is back to active without recovery delay. in the standby mode the outputs are in the high imped- ance state, independent of the oe# input. kh29lv320c t/b is capable to provide the automatic standby mode to restrain power consumption during read- out of data. this mode can be used effectively with an application requested low power consumption such as handy terminals. to active this mode, kh29lv320c t/b automatically switch themselves to low power mode when kh29lv320c t/b addresses remain stable during access time of tacc+30ns. it is not necessary to control ce#, we#, and oe# on the mode. under the mode, the current con- sumed is typically 0.2ua (cmos level).
12 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b output disable with the oe# input at a logic high level (vih), output from the devices are disabled. this will cause the output pins to be in a high impedance state. reset# operation the reset# pin provides a hardware method of reset- ting the device to reading array data. when the reset# pin is driven low for at least a period of trp, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write com- mands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity current is reduced for the duration of the reset# pulse. when reset# is held at vss0.3v, the device draws cmos standby current (icc4). if reset# is held at vil but not within vss0.3v, the standby current will be greater. the reset# pin may be tied to system reset circuitry. a system reset would that also reset the flash memory, enabling the system to read the boot-up firm-ware from the flash memory. if reset# is asserted during a program or erase opera- tion, the ry/by# pin remains a "0" (busy) until the inter- nal reset operation is complete, which requires a time of tready (during embedded algorithms). the system can thus monitor ry/by# to determine whether the reset op- eration is complete. if reset# is asserted when a pro- gram or erase operation is not executing (ry/by# pin is "1"), the reset operation is completed within a time of tready (not during embedded algorithms). the system can read data trh after the reset# pin returns to vih. refer to the ac characteristics tables for reset# pa- rameters and to figure 14 for the timing diagram. sector group protect operation the kh29lv320c t/b features hardware sector group protection. this feature will disable both program and erase operations for these sector group protected. sec- tor protection can be implemented via two methods. the primary method requires vid on the reset# only. this method can be implemented either in-system or via programming equipment. this method uses standard mi- croprocessor bus cycle timing. refer to figure 13 for tim- ing diagram and figure 14 illustrates the algorithm for the sector group protection operation. the alternate method intended only for programming equipment, must force vid on address pin a9 and con- trol pin oe#, (suggest vid = 12v) a6 = vil and ce# = vil(see table 2). programming of the protection circuitry begins on the falling edge of the we# pulse and is termi- nated on the rising edge. contact mxic for details. to verify programming of the protection circuitry, the pro- gramming equipment must force v id on address pin a9 ( with ce# and oe# at vil and we# at vih). when a1=1, it will produce a logical "1" code at device output q0 for a protected sector. otherwise the device will produce 00h for the unprotected sector. in this mode, the addresses, except for a1, are don't care. address locations with a1= vil are reserved to read manufacturer and device codes.(read silicon id) it is also possible to determine if the group is protected in the system by writing a read silicon id command. performing a read operation with a1=vih, it will produce a logical "1" at q0 for the protected sector. chip unprotect operation the kh29lv320c t/b also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. it is recommended to protect all sectors before activating chip unprotect mode. the primary method requires vid on the reset# only. this method can be implemented either in-system or via programming equipment. this method uses standard microprocessor bus cycle timing. refer to figure 13 for timing diagram and figure 14 illustrates the algorithm for the sector group protection operation. the alternate method intended only for programming equipment, must force vid on address pin a9 and con- trol pin oe#, (suggest vid = 12v) a6 = vil and ce# = vil(see table 2). programming of the protection circuitry begins on the falling edge of the we# pulse and is termi- nated on the rising edge. contact mxic for details.
13 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b it is also possible to determine if the chip is unprotected in the system by writing the read silicon id command. performing a read operation with a1=vih, it will produce 00h at data outputs(q0-q7) for an unprotected sector. it is noted that all sectors are unprotected after the chip unprotect algorithm is completed. temporary sector group unprotect opera- tion this feature allows temporary unprotection of previously protected sector to change data in-system. the tempo- rary sector unprotect mode is activated by setting the reset# pin to v id (11.5v-12.5v). during this mode, for- merly protected sectors can be programmed or erased as un-protected sector. once v id is remove from the reset# pin, all the previously protected sectors are pro- tected again. write protect (wp#) the write protect function provides a hardware method to protect boot sectors without using v id . if the system asserts vil on the wp#/acc pin, the de- vice disables program and erase functions in the two "out- ermost" 8 kbyte boot sectors independently of whether those sectors were protected or unprotected using the method described in sector/sector group protection and chip unprotection". the two outermost 8 kbyte boot sec- tors are the two sectors containing the lowest addresses in a bottom-boot-configured device, or the two sectors containing the highest addresses in a top-boot-configured device. if the system asserts vih on the wp#/acc pin, the de- vice reverts to whether the two outermost 8k byte boot sectors were last set to be protected or unprotected. that is, sector protection or unprotection for these two sectors depends on whether they were last protected or unpro- tected using the method described in "sector/sector group protection and chip unprotection". note that the wp#/acc pin must not be left floating or unconnected; inconsistent behavior of the device may result. automatic select operation flash memories are intended for use in applications where the local cpu alters memory contents. as such, manu- facturer and device codes must be accessible while the device resides in the target system. prom program- mers typically access signature codes by raising a9 to a high voltage. however, multiplexing high voltage onto address lines is not generally desired system design prac- tice. kh29lv320c t/b provides hardware method to access the automatic select operation. this method requires v id on a9 pin, vil on ce#, oe#, a6, and a1 pins. when applying vil on a0 pin, the device will output mxic's manufacture code of c2h. when applying vih on a0 pin, the device will output kh29lv320c t/b device code of 22a7h and 22a8h. verify sector group protect status opera- tion kh29lv320c t/b provides hardware method for sector group protect status verify. this method requires v id on a9 pin, vih on we# and a1 pins, vil on ce#, oe#, a6, and a0 pins, and sector address on a12 to a20 pins. when the identified sector is protected, the device will output 01h. when the identified sector is not protect, the device will output 00h. security sector flash memory region the security sector (security sector) feature provides a flash memory region that enables permanent part iden- tification through an electronic serial number (esn). the security sector is 64 kbytes (32 kwords) in length, and uses a security sector indicator bit (q7) to indicate whether or not the security sector is locked when shipped from the factory. this bit is per-manently set at the fac- tory and cannot be changed, which prevents cloning of a factory locked part. this ensures the security of the esn once the product is shipped to the field. mxic offers the device with the security sector either factory locked or customer lockable. the factory-locked version is always protected when shipped from the fac- tory, and has the security on silicon sector (security sector) indicator bit permanently set to a "1". the cus- tomer-lockable version is shipped with the unprotected, allowing customers to utilize the that sector in any man- ner they choose. the customer-lockable version has the security on silicon sector (security sector) indicator bit permanently set to a "0". thus, the security sector indi- cator bit prevents customer-lockable devices from being
14 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b used to replace devices that are factory locked. the system accesses the security sector through a com- mand sequence (see "enter security sector/exit secu- rity sector command sequence"). after the system has written the enter security sector command se-quence, it may read the security sector by using the ad-dresses normally occupied by the boot sectors. this mode of op- eration continues until the system issues the exit secu- rity sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending commands to the boot sectors. factory locked: security sector programmed and protected at the factory in a factory locked device, the security sector is pro- tected when the device is shipped from the factory. the security sector cannot be modified in any way. the de- vice is available preprogrammed with one of the follow- ing: a random, secure esn only. in devices that have an esn, a bottom boot device will have the 16-byte (8-word) esn in the lowest address- able memory area starting at 00000h and ending at 0000fh (00007h). in the top boot device the starting address of the esn will be at the bottom of the lowest 8 kbyte (4 kword) boot sector starting at 3f0000h (1f8000h) and ending at 3f000fh (1f8007h). customer lockable: security sector not pro- grammed or protected at the factory if the security feature is not required, the security sec- tor can be treated as an additional flash memory space, expanding the size of the available flash array by 64 kbytes (32 kwords). the security sector can be read, programmed, and erased as often as required. the se- curity sector area can be protected using one of the following procedures: write the three-cycle enter security region command sequence, and then follow the in-system sector group protect algorithm as shown in figure 14, except that reset# may be at either vih or v id . this allows in-sys- tem protection of the without raising any device pin to a high voltage. note that this method is only applicable to the security sector. write the three-cycle enter security region command sequence, and then use the alternate method of sector protection described in the "sector/sector block protec- tion and unprotection section. once the security sector is locked and verified, the sys- tem must write the exit security sector region com- mand sequence to return to reading and writing the re- mainder of the array. the security sector protection must be used with cau- tion since, once protected, there is no procedure avail- able for unprotecting the security sector area and none of the bits in the security sector memory space can be modified in any way. data protection the kh29lv320c t/b is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. during power up the device automatically re- sets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful comple- tion of specific command sequences. the device also incorporates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down tran- sition or system noise. low vcc write inhibit when vcc is less than vlko the device does not ac- cept any write cycles. this protects data during vcc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until vcc is greater than vlko. the system must provide the proper signals to the control pins to prevent unintentional write when vcc is greater than vlko. write pulse "glitch" protection noise pulses of less than 5ns (typical) on oe#, ce# or we# will not initiate a write cycle.
15 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b logical inhibit writing is inhibited by holding any one of oe# = vil, ce# = vih or we# = vih. to initiate a write cycle ce# and we# must be a logical zero while oe# is a logical one. power-up sequence the kh29lv320c t/b powers up in the read only mode. in addition, the memory contents may only be altered after successful completion of the predefined command sequences. power-up write inhibit if we#=ce#=vil and oe#=vih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. power supply decoupling in order to reduce power switching effect, each device should have a 0.1uf ceramic capacitor connected be- tween its vcc and gnd. software command definitions device operations are selected by writing specific ad- dress and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. table 3 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. either of the two reset command sequences will reset the device (when applicable). all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data are latched on rising edge of we# or ce#, whichever happens first.
16 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b first bus second bus third bus fourth bus fifth bus sixth bus command bus cycle cycle cycle cycle cycle cycle cycles addr data addr data addr data addr data addr data addr data read(note 5) 1 ra rd reset(note 4) 1 xxx f0 automatic select(note 5) manufacturer id word 4 555 aa 2aa 55 555 90 x00 c2h byte 4 aaa aa 555 55 aaa 90 x00 c2h device id word 4 555 aa 2aa 55 555 90 x01 id byte 4 aaa aa 555 55 aaa 90 x02 security sector factory word 4 555 aa 2aa 55 555 90 x03 99/19 protect verify (note 6) byte 4 aaa aa 555 55 aaa 90 x06 sector protect verify word 4 555 aa 2aa 55 555 90 (sa)x02 00/01 (note 7) byte 4 aaa aa 555 55 aaa 90 (sa)x04 enter security sector word 3 555 aa 2aa 55 555 88 region byte 3 aaa aa 555 55 aaa 88 exit security sector word 4 555 aa 2aa 55 555 90 xxx 00 byte 4 aaa aa 555 55 aaa 90 xxx 00 program word 4 555 aa 2aa 55 555 a0 pa pd byte 4 aaa aa 555 55 aaa a0 pa pd chip erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase word 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 byte 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 cfi query (note 8) word 1 55 98 byte 1 aa 98 erase suspend(note 9) 1 sa b0 erase resume(note 10) 1 sa 30 table 3. kh29lv320c t/b command definitions legend: x=don't care ra=address of the memory location to be read. rd=data read from location ra during read operation. pa=address of the memory location to be programmed. addresses are latched on the falling edge of the we# or ce# pulse. pd=data to be programmed at location pa. data is latched on the rising edge of we# or ce# pulse. sa=address of the sector to be erased or verified. address bits a20-a12 uniquely select any sector. id=22a7h(top), 22a8h(bottom) notes: 1. see table 1 for descriptions of bus operations. 2. all values are in hexadecimal. 3. except when reading array or automatic select data, all bus cycles are write operation. 4. the reset command is required to return to the read mode when the device is in the automatic select mode or if q5 goes high. 5. the fourth cycle of the automatic select command sequence is a read cycle. 6. the data is 99h for factory locked and 19h for not factory locked. 7. the data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. in the third cycle of the command sequence, address bit a20=0 to verify sectors 0~31, a20=1 to verify sectors 32~70 for top boot device. 8. command is valid when device is ready to read array data or when device is in automatic select mode. 9. the system may read and program functions in non-erasing sectors, or enter the automatic select mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 10. the erase resume command is valid only during the erase suspend mode.
17 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b reading array data the device is automatically set to reading array data af- ter device power-up. no commands are required to re- trieve data. the device is also ready to read array data after completing an automatic program or automatic erase algorithm. after the device accepts an erase suspend command, the device enters the erase suspend mode. the sys- tem can read array data using the standard read tim- ings, except that if it reads at an address within erase- suspended sectors, the device outputs status data. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same exception. see erase suspend/erase resume commands ? for more information on this mode. the system must issue the reset command to re-en- able the device for reading array data if q5 goes high during an active program or erase operation, or while in the automatic select mode. see the "reset command" section, next. reset command writing the reset command to the device resets the de- vice to reading array data. address bits are don't care for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence before programming begins. this resets the device to reading array data (also applies to programming in erase sus- pend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an automatic select command se- quence. once in the automatic select mode, the reset command must be written to return to reading array data (also applies to automatic select during erase suspend). if q5 goes high during a program or erase operation, writ- ing the reset command returns the device to reading ar- ray data (also applies during erase suspend). automatic select command sequence the automatic select command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is pro-tected. table 2 shows the address and data requirements. this method is an alternative to that shown in table 3, which is intended for eprom programmers and requires v id on address bit a9. the automatic select command sequence is initiated by writ-ing two unlock cycles, followed by the automatic select command. the device then enters the automatic select mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h retrieves the manufacturer code. a read cycle at address xx01h in word mode (or xx02h in byte mode) returns the device code. a read cycle containing a sector address (sa) and the address 02h on a7-a0 in word mode (or the address 04h on a6-a-1 in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. refer to table 1 for valid sector addresses. the system must write the reset command to exit the automatic select mode and return to reading array data. enter security sector & exit security sec- tor command sequence the security sector provides a secured area which con- tains a random, sixteen-byte electronic serial number.(esn) the system can access the security sector area by is- suing the three-cycle "enter security sector command sequence. the device continues to access the security section area until the system issues the four-cycle exit security sector command sequence. the exit security sector command sequence returns the device to normal operation. byte/word program command sequence the device programs one byte/word of data for each program operation. the command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the
18 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b device automatically generates the program pulses and verifies the programmed cell margin. table 3 shows the address and data requirements for the byte/word program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using q7, q6, or ry/ by#. see "write operation status" for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the programming operation. the byte/word program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a "0" back to a "1". attempting to do so may cause the device to set q5 to "1", or cause the data# polling pins a0 a1 q7 q6 q5 q4 q3 q2 q1 q0 code (hex) manufacture code vil vil 1 1 0 0 0 0 1 0 c2h device code for kh29lv320ct vih vil 1 0 1 0 0 1 1 1 22a7h device code for KH29LV320CB vih vil 1 0 1 0 1 0 0 0 22a8h table 4. silicon id code automatic chip/sector erase command the device does not require the system to preprogram prior to erase. the automatic erase algorithm automati- cally preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. table 3 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the automatic erase algorithm are ignored. note that a hard-ware reset during the chip erase operation immediately terminates the operation. the chip erase command sequence should algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still "0". only erase operations can convert a "0" to a "1". setup automatic chip/sector erase chip erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command 80h. two more "unlock" write cycles are then followed by the chip erase command 10h, or the sector erase command 30h. the kh29lv320c t/b contains a silicon-id-read opera- tion to supplement traditional prom programming meth- odology. the operation is initiated by writing the read sili- con id command sequence into the command register. following the command write, a read cycle with a1=vil,a0=vil retrieves the manufacturer code of c2h. a read cycle with a1=vil, a0=vih returns the device code of a7h/a8h for kh29lv320c t/b. be reinitiated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase op- eration by using q7, q6, q2, or ry/by#. see "write op- eration status" for information on these status bits. when the automatic erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 5 illustrates the algorithm for the erase opera-tion. see the erase/program operations tables in "ac char- acteristics" for parameters, and to figure 4 for timing diagrams.
19 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b sector erase commands the device does not require the system to entirely pre-program prior to executing the automatic set-up sector erase command and automatic sector erase command. upon executing the automatic sector erase command, the device will automatically program and verify the sector(s) memory for an all- zero data pattern. the system is not required to provide any control or timing during these operations. when the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. the erase and verify operations are complete when the data on q7 is "1" and the data on q6 stops toggling for two consecutive read cycles, at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. when using the automatic sector erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). sector erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the set-up command 80h. two more "unlock" write cycles are then followed by the sector erase command 30h. the sector address is latched on the falling edge of we# or ce#, whichever happens later , while the command(data) is latched on the rising edge of we# or ce#, whichever happens first. sector addresses selected are loaded into internal register on the sixth falling edge of we# or ce#, whichever happens later. each successive sector load cycle started by the falling edge of we# or ce#, whichever happens later must begin within 50us from the rising edge of the preceding we# or ce#, whichever happens first. otherwise, the loading period ends and internal auto sector erase cycle starts. (monitor q3 to determine if the sector erase timer window is still open, see section q3, sector erase timer.) any command other than sector erase(30h) or erase suspend(b0h) during the time- out period resets the device to read mode. erase suspend this command only has meaning while the state ma- chine is executing automatic sector erase operation, and therefore will only be responded during automatic sector erase operation. when the erase suspend com- mand is issued during the sector erase operation, the device requires a maximum 20us to suspend the sector erase operation. however, when the erase suspend com- mand is written during the sector erase time-out, the de- vice immediately terminates the time-out period and sus- pends the erase operation. after this command has been executed, the command register will initiate erase sus- pend mode. the state machine will return to read mode automatically after suspend is ready. at this time, state machine only allows the command register to respond to the erase resume, program data to, or read data from any sector not selected for erasure. the system can use q7, or q6 and q2 together, to determine if a sector is actively erasing or is erase-suspended. the system can determine the status of the program operation using the q7 or q6 status bits, just as in the standard program operation. after an erase-suspend pro- gram operation is complete, the system can once again read array data within non-suspended blocks. erase resume this command will cause the command register to clear the suspend state and return back to sector erase mode but only if an erase suspend command was previously issued. erase resume will not have any effect in all other conditions. another erase suspend command can be written after the chip has resumed erasing.
20 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b table 5. write operation status notes: 1. performing successive read operations from the erase-suspended sector will cause q2 to toggle. 2. performing successive read operations from any address will cause q6 to toggle. 3. reading the byte/word address being programmed while in the erase-suspend program mode will indicate logic "1" at the q2 bit. however, successive reads from the erase-suspended sector will cause q2 to toggle. write operation status the device provides several bits to determine the sta- tus of a write operation: q2, q3, q5, q6, q7, and ry/ by#. table 5 and the following subsections describe the functions of these bits. q7, ry/by#, and q6 each offer a method for determining whether a program or erase op- eration is complete or in progress. these three bits are discussed first. status q7 q6 q5 q3 q2 ry/ note1 note2 by# byte/word program in auto program algorithm q7# toggle 0 n/a no 0 toggle auto erase algorithm 0 toggle 0 1 toggle 0 erase suspend read 1 no 0 n/a toggle 1 (erase suspended sector) toggle in progress erase suspended mode erase suspend read data data data data data 1 (non-erase suspended sector) erase suspend program q7# toggle 0 n/a n/a 0 byte/word program in auto program algorithm q7# toggle 1 n/a no 0 toggle exceeded time limits auto erase algorithm 0 toggle 1 1 toggle 0 erase suspend program q7# toggle 1 n/a n/a 0
21 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b q7: data# polling the data# polling bit, q7, indicates to the host system whether an automatic algorithm is in progress or com- pleted, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command sequence. during the automatic program algorithm, the device out- puts on q7 the complement of the datum programmed to q7. this q7 status also applies to programming dur- ing erase suspend. when the automatic program algo- rithm is complete, the device outputs the datum pro- grammed to q7. the system must provide the program address to read valid status information on q7. if a pro- gram address falls within a protected sector, data# poll- ing on q7 is active for approximately 1 us, then the de- vice returns to reading array data. during the automatic erase algorithm, data# polling pro- duces a "0" on q7. when the automatic erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a "1" on q7. this is analo- gous to the complement/true datum out-put described for the automatic program algorithm: the erase function changes all the bits in a sector to "1" prior to this, the device outputs the "complement," or "0". the system must provide an address within any of the sectors selected for erasure to read valid status information on q7. after an erase command sequence is written, if all sec- tors selected for erasing are protected, data# polling on q7 is active for approximately 100 us, then the device returns to reading array data. if not all selected sectors are protected, the automatic erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. when the system detects q7 has changed from the complement to true data, it can read valid data at q7-q0 on the following read cycles. this is because q7 may change asynchronously with q0-q6 while output enable (oe#) is asserted low. q6:toggle bit i toggle bit i on q6 indicates whether an automatic pro- gram or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# or ce#, whichever happens first pulse in the command sequence (prior to the program or erase operation), and during the sector time-out. during an automatic program or erase algorithm opera- tion, successive read cycles to any address cause q6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, q6 stops toggling. after an erase command sequence is written, if all sec- tors selected for erasing are protected, q6 toggles for 100us and returns to reading array data. if not all se- lected sectors are protected, the automatic erase algo- rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use q6 and q2 together to determine whether a sector is actively erasing or is erase suspended. when the device is actively erasing (that is, the auto- matic erase algorithm is in progress), q6 toggling. when the device enters the erase suspend mode, q6 stops toggling. however, the system must also use q2 to de- termine which sectors are erasing or erase-suspended. alternatively, the system can use q7. if a program address falls within a protected sector, q6 toggles for approximately 2us after the program com- mand sequence is written, then returns to reading array data. q6 also toggles during the erase-suspend-program mode, and stops toggling once the automatic program algo- rithm is complete. table 5 shows the outputs for toggle bit i on q6. q2:toggle bit ii the "toggle bit ii" on q2, when used with q6, indicates whether a particular sector is actively erasing (that is, the automatic erase algorithm is in process), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# or ce#, whichever happens first pulse in the command sequence. q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. q6, by compari-
22 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b son, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sec- tors are selected for erasure. thus, both status bits are required for sectors and mode information. refer to table 5 to compare outputs for q2 and q6. reading toggle bits q6/ q2 whenever the system initially begins reading toggle bit status, it must read q7-q0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on q7-q0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of q5 is high (see the section on q5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as q5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase opera- tion. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that system initially determines that the toggle bit is toggling and q5 has not gone high. the system may continue to monitor the toggle bit and q5 through successive read cycles, determining the sta- tus as described in the previous paragraph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the al- gorithm when it returns to determine the status of the operation. q5:program/erase timing q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). under these conditions q5 will produce a "1". this time-out condition indicates that the program or erase cycle was not suc- cessfully completed. data# polling and toggle bit are the only operating functions of the device under this con- dition. if this time-out condition occurs during sector erase op- eration, it specifies that a particular sector is bad and it may not be reused. however, other sectors are still func- tional and may be used for the program or erase opera- tion. the device must be reset to use other sectors. write the reset command sequence to the device, and then execute program or erase command sequence. this al- lows the system to continue to use the other active sec- tors in the device. if this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or com- bination of sectors are bad. if this time-out condition occurs during the byte/word pro- gramming operation, it specifies that the entire sector containing that byte/word is bad and this sector maynot be reused, (other sectors are still functional and can be reused). the time-out condition may also appear if a user tries to program a non blank location without erasing. in this case the device locks out and never completes the au- tomatic algorithm operation. hence, the system never reads a valid data on q7 bit and q6 never stops toggling. once the device has exceeded timing limits, the q5 bit will indicate a "1". please note that this is not a device failure condition since the device was incorrectly used. the q5 failure condition may appear if the system tries to program a "1" to a location that is previously pro- grammed to "0". only an erase operation can change a "0" back to a "1". under this condition, the device halts the operation, and when the operation has exceeded the timing limits, q5 produces a "1". q3:sector erase timer after the completion of the initial sector erase command sequence, the sector erase time-out will begin. q3 will remain low until the time-out is complete. data# polling and toggle bit are valid after the initial sector erase com- mand sequence. if data# polling or the toggle bit indicates the device has been written with a valid erase command, q3 may be used to determine if the sector erase timer window is still open. if q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is
23 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b completed as indicated by data# polling or toggle bit. if q3 is low ("0"), the device will accept additional sector erase commands. to insure the command has been ac- cepted, the system software should check the status of q3 prior to and following each subsequent sector erase command. if q3 were high on the second status check, the command may not have been accepted. if the time between additional erase commands from the system can be less than 50us, the system need not to monitor q3. ry/by#:ready/busy# output the ry/by# is a dedicated, open-drain output pin that indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to vcc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is ready to read array data (includ-ing during the erase suspend mode), or is in the standby mode. query command and common flash inter- face (cfi) mode kh29lv320c t/b is capable of operating in the cfi mode. this mode all the host system to determine the manu- facturer of the device such as operating parameters and configuration. two commands are required in cfi mode. query command of cfi mode is placed first, then the reset command exits cfi mode. these are described in table 3. the single cycle query command is valid only when the device is in the read mode, including erase suspend, standby mode, and automatic select mode; however, it is ignored otherwise. the reset command exits from the cfi mode to the read mode, or erase suspend mode, or automatic se- lect mode. the command is valid only when the device is in the cfi mode.
24 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b table 6-1. cfi mode: identification data values (all values in these tables are in hexadecimal) description address (h) address (h) data (h) (word mode) (byte mode) query-unique ascii string "qry" 10 20 0051 11 22 0052 12 24 0059 primary vendor command set and control interface id code 13 26 0002 14 28 0000 address for primary algorithm extended query table 15 2a 0040 16 2c 0000 alternate vendor command set and control interface id code (none) 17 2e 0000 18 30 0000 address for secondary algorithm extended query table (none) 19 32 0000 1a 34 0000 table 6-2. cfi mode: system interface data values description address (h) address (h) data (h) (word mode) (byte mode) vcc supply, minimum (2.7v) 1b 36 0027 vcc supply, maximum (3.6v) 1c 38 0036 vpp supply, minimum (none) 1d 3a 0000 vpp supply, maximum (none) 1e 3c 0000 typical timeout for single word/byte write (2 n us) 1f 3e 0004 typical timeout for maximum size buffer write (2 n us) (not supported) 20 40 0000 typical timeout for individual sector erase (2 n ms) 21 42 000a typical timeout for full chip erase (2 n ms) 22 44 0000 maximum timeout for single word/byte write times (2 n x typ) 23 46 0005 maximum timeout for maximum size buffer write times (2 n x typ) 24 48 0000 maximum timeout for individual sector erase times (2 n x typ) 25 4a 0004 maximum timeout for full chip erase times (not supported) 26 4c 0000
25 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b table 6-3. cfi mode: device geometry data values description address (h) address (h) data (h) (word mode) (byte mode) device size (2 n bytes) 27 4e 0016 flash device interface code (02=asynchronous x8/x16) 28 50 0002 29 52 0000 maximum number of bytes in multi-byte write (not supported) 2a 54 0000 2b 56 0000 number of erase sector regions 2c 58 0002 erase sector region 1 information 2d 5a 0007 [2e,2d] = # of same-size sectors in region 1-1 2e 5c 0000 [30, 2f] = sector size in multiples of 256-bytes 2f 5e 0020 30 60 0000 erase sector region 2 information 31 62 003e 32 64 0000 33 66 0000 34 68 0001 erase sector region 3 information 35 6a 0000 36 6c 0000 37 6e 0000 38 70 0000 erase sector region 4 information 39 72 0000 3a 74 0000 3b 76 0000 3c 78 0000
26 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b table 6-4. cfi mode: primary vendor-specific extended query data values description address (h) address (h) data (h) (word mode) (byte mode) query-unique ascii string "pri" 40 80 0050 41 82 0052 42 84 0049 major version number, ascii 43 86 0031 minor version number, ascii 44 88 0031 address sensitive unlock (0=required, 1= not required) 45 8a 0000 erase suspend (2= to read and write) 46 8c 0002 sector protect (n= # of sectors/group) 47 8e 0004 temporary sector unprotect (1=supported) 48 90 0001 sector protect/chip unprotect scheme 49 92 0004 simultaneous r/w operation (0=not supported) 4a 94 0000 burst mode type (0=not supported) 4b 96 0000 page mode type (0=not supported) 4c 98 0000 acc (acceleration) supply minimum 4d 9a 00b5 (0=not supported, d7-d4:volt, d3-d0:100mv acc (acceleration) supply maximum 4e 9c 00c5 (0=not supported, d7-d4:volt, d3-d0:100mv top/bottom boot sector flag 4f 9e 000x 02h=bottom boot device, 03h=top boot device
27 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . ..... -65 o c to +150 o c ambient temperature with power applied. . . . . . . . . . . . . .... -65 o c to +125 o c voltage with respect to ground vcc (note 1) . . . . . . . . . . . . . . . . . -0.5 v to +4.0 v a9, oe#, and reset# (note 2) . . . . . . . . . . . ....-0.5 v to +12.5 v all other pins (note 1) . . . . . . . -0.5 v to vcc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is -0.5 v. during voltage transitions, input or i/o pins may over- shoot vss to -2.0 v for periods of up to 20ns. maxi- mum dc voltage on input or i/o pins is vcc +0.5 v. during voltage transitions, input or i/o pins may over- shoot to vcc +2.0 v for periods up to 20 ns. 2. minimum dc input voltage on pins a9, oe#, and re- set# is -0.5 v. during voltage transitions, a9, oe#, and reset# may overshoot vss to -2.0 v for periods of up to 20 ns. maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. operating ratings commercial (c) devices ambient temperature (t a ). . . . . . . . . . . . 0 c to +70 c industrial (i) devices ambient temperature (t a ). . . . . . . . . . -40 c to +85 c v cc supply voltages v cc for full voltage range. . . . . . . . . . . +2.7 v to 3.6 v operating ranges define those limits between which the functionality of the device is guaranteed.
28 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b notes: 1. on the wp#/acc pin only, the maximum input load current when wp#/acc = vil is 5.0ua / vih is 3.0ua. 2. maximum icc specifications are tested with vcc = vcc max. 3. the icc current listed is typically is less than 2 ma/mhz, with oe# at vih. typical specifications are for vcc = 3.0v. 4. icc active while embedded erase or embedded program is in progress. 5. automatic sleep mode enables the low power mode when addresses remain stable for tacc + 30 ns. typical sleep mode current is 200 na. 6. not 100% tested. dc characteristics vcc=2.7v~3.6v para- description test conditions ta=0 c to 70 c ta=-40 c to 85 c meter min typ max min typ max unit ili input load current vin = vss to vcc, 1.0 1.0 ua (note 1) vcc = vcc max ilit a9 input load current vcc = vcc max, 35 45 ua a9=12.5v ilo output leakage current v out = vss to vcc , 1.0 1.0 ua vcc = vcc max icc1 vcc active read current ce#=vil, 5 mhz 10 16 10 16 ma (notes 2, 3) oe#=vih 1 mhz 2 4 2 4 ma icc2 vcc active write current ce#=vil , oe# = vih, 15 30 15 30 ma (notes 2, 4, 6) we#=vil icc3 vcc standby current ce#, reset#, 0.2 15 0.2 15 ua (note 2) wp#/acc = vcc 0.3v icc4 vcc reset current (note 2) reset# = vss 0.3v, 0.2 15 0.2 15 ua wp#/acc= vcc 0.3v icc5 automatic sleep mode vih = vcc 0.3v; 0.2 15 0.2 15 ua (notes 2,5) vil = vss 0.3v, wp#/acc=vcc 0.3v iacc wp#/acc accelerated ce#=vil, wp#/acc pin 5 10 5 10 ma program current, word or byte oe#=vih vcc pin 15 30 15 30 ma vil input low voltage -0.5 0.8 -0.5 0.8 v vih input high voltage 0.7xvcc vcc+0.3 0.7xvcc vcc+0.3 v vhh voltage for wp#/acc sector vcc = 3.0 v 10% 11.5 12.5 11.5 12.5 v protect/unprotect and program acceleration vid voltage for automatic select vcc = 3.0 v 10% 11.5 12.5 11.5 12.5 v and temporary sector unprotect vol output low voltage iol=4.0ma, 0.45 0.45 v vcc=vcc min voh1 output high voltage ioh=-2.0ma, 0.85vcc 0.85vcc v vcc=vcc min voh2 ioh=-100ua, vcc-0.4 vcc-0.4 v vcc = vcc min vlko low vcc lock-out voltage 1.4 2.1 1.4 2.1 v (note 6)
29 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b switching test circuits test specifications test condition 70 90 unit output load 1 ttl gate output load capacitance,cl 30 100 pf (including jig capacitance) input rise and fall times 5 ns input pulse levels 0.0-3.0 v input timing measurement 1.5 v reference levels output timing measurement 1.5 v reference levels 1.5v 1.5v measurement level 3.0v 0.0v output input switching test waveforms device under test diodes=in3064 or equivalent cl 6.2k ohm 1.6k ohm +3.3v waveform inputs outputs steady changing from h to l changing from l to h don't care, any change permitted changing, state unknown does not apply center line is high impedance state(high z) key to switching waveforms
30 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b symbol description condition 70 90 unit tacc address to output delay ce#=vil max 70 90 ns oe#=vil tce chip enable to output delay oe#=vil max 70 90 ns toe output enable to output delay max 40 40 ns tdf oe# high to output float(note1) max 30 30 ns toh output hold time of from the rising edge of min 0 0 ns address, ce# or oe# whichever happens first trc read cycle time (note 1) min 70 90 ns twc write cycle time (note 1) min 70 90 ns tcwc command write cycle time(note 1) min 70 90 ns tas address setup time min 0 0 ns tah address hold time min 45 45 ns tds data setup time min 45 45 ns tdh data hold time min 0 0 ns tvcs vcc setup time(note 1) min 50 50 ns tcs chip enable setup time min 0 0 ns tch chip enable hold time min 0 0 ns toes output enable setup time (note 1) min 0 0 ns toeh output enable hold time (note 1) read min 0 0 ns toggle & min 10 10 ns data# polling twes we# setup time min 0 0 ns tweh we# hold time min 0 0 ns tcep ce# pulse width min 45 45 ns tceph ce# pulse width high min 30 30 ns twp we# pulse width min 35 35 ns twph we# pulse wi dth high min 30 30 ns tbusy program/erase valid to ry/by# delay max 90 90 ns tghwl read recovery time before write min 0 0 ns tghel read recovery time before write min 0 0 ns twhwh1 programming operation byte typ 9 9 us word typ 11 11 us accelerated programming operation word or typ 7 7 us byte twhwh2 sector erase operation typ 0.9 0.9 sec tbal sector address hold time max 50 50 us notes: 1.not 100% tested ac characteristics ta=-40 c to 85 c, vcc=2.7v~3.6v
31 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 1. command write operation addresses ce# oe# we# din tds tah data tdh tcs tch tcwc twph twp toes tas vcc 3v vih vil vih vil vih vil vih vil vih vil add valid
32 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b read/reset operation figure 2. read timing waveforms addresses ce# oe# tacc we# vih vil vih vil vih vil vih vil voh vol high z high z data valid toe toeh tdf tce trc outputs toh add valid
33 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 3. reset# timing waveform ac characteristics parameter description test setup all speed options unit tready1 reset# pin low (during automatic algorithms) max 20 us to read or write (see note) tready2 reset# pin low (not during automatic max 500 ns algorithms) to read or write (see note) trp1 reset# pulse width (during automatic algorithms) min 10 us trp2 reset# pulse width (not during automatic algorithms) min 500 ns trh reset# high time before read(see note) min 70 ns trb1 r y/by# recovery time(to ce#, oe# go low) min 0 ns trb2 r y/by# recovery time(to we# go low) min 50 ns note:not 100% tested trh trb1 tready1 trp2 trp1 tready2 ry/by# ce#, oe# reset# reset timing not during automatic algorithms reset timing during automatic algorithms ry/by# ce#, oe# trb2 we# reset#
34 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b erase/program operation figure 4. automatic chip erase timing waveform twc address oe# ce# 55h 2aah sa 10h in progress complete va va note: sa=sector address(for sector erase), va=valid address for reading status data(see "write operation status"). tas tah 555h for chip erase tghwl tch twp tds tdh twhwh2 read status data erase command sequence(last two cycle) tbusy trb tcs twph tvcs we# data ry/by# vcc
35 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 5. automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes write data 10h address 555h write data 55h address 2aah data = ffh ? yes auto erase completed data poll from system no
36 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 6. automatic sector erase timing waveform twc address oe# ce# 55h 2aah sector address 1 sector address 0 30h in progress complete va va 30h note: sa=sector address(for sector erase), va=valid address for reading status data(see "write operation status"). sector address n tas tah tbal tghwl tch twp tds tdh twhwh2 read status data erase command sequence(last two cycle) tbusy trb tcs twph tvcs we# data ry/by# vcc 30h
37 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 7. automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h write data 30h sector address write data 55h address 2aah auto sector erase completed data poll from system yes no data=ffh? last sector to erase ? no yes
38 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 8. erase suspend/resume flowchart start write data b0h toggle bit checking q6 not toggled erase suspend yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no yes yes no erase resume
39 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 9. automatic program timing waveforms figure 10. accelerated program timing diagram twc address oe# ce# a0h 555h pa pd status dout pa pa note: 1.pa=program address, pd=program data, dout is the true data the program address tas tah tghwl tch twp tds tdh twhwh1 read status data (last two cycle) program command sequence(last two cycle) tbusy trb tcs twph tvcs we# data ry/by# vcc wp#/acc tvhh vhh (11.5v ~ 12.5v) vil or vih vil or vih tvhh
40 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 11. ce# controlled write timing waveform twc twh tghel twhwh1 or 2 tcp address we# oe# ce# data q7 pa data# polling dout reset# ry/by# notes: 1. pa=program address, pd=program data, dout=data out, q7=complement of data written to device. 2. figure indicates the last two bus cycles of the command sequence. tah tas pa for program sa for sector erase 555 for chip erase trh tdh tds tws a0 for program 55 for erase tcph tbusy pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase
41 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 12. automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes verify data ok ? yes auto program completed data poll from system increment address last address ? no no
42 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b sector group protect/chip unprotect figure 13. sector group protect/chip unprotect waveform (reset# control) note: 1. for sector group protect a6=0, a1=1, a0=0 ; for chip unprotect a6=1, a1=1, a0=0 sector group protect: 150us chip unprotect: 15ms 1us vid vih data sa, a6 a1, a0 ce# we# oe# valid (note2) valid (note2) valid (note2) status sector group protect or chip unprotect 40h 60h 60h verify reset#
43 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 14. in-system sector group protect/chip unprotect algorithms with reset#=vid start plscnt=1 reset#=vid wait 1us set up sector address sector protect: write 60h to sector address with a6=0, a1=1, a0=0 wait 150us verify sector protect: write 40h to sector address with a6=0, a1=1, a0=0 read from sector address with a6=0, a1=1, a0=0 reset plscnt=1 remove vid from reset# write reset command sector protect algorithm chip unprotect algorithm sector protect complete remove vid from reset# write reset command chip unprotect complete device failed temporary sector unprotect mode increment plscnt increment plscnt first write cycle=60h? set up first sector address protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address chip unprotect: write 60h to sector address with a6=1, a1=1, a0=0 time out timing (note 1) verify sector unprotect: write 40h to sector address with a6=1, a1=1, a0=0 read from sector address with a6=1, a1=1, a0=0 data=01h? plscnt=25? device failed start plscnt=1 reset#=vid wait 1us first write cycle=60h? all sectors protected? data=00h? plscnt=1000? last sector verified? ye s ye s ye s no no no ye s ye s ye s ye s ye s ye s no no no no no no protect another sector? reset plscnt=1 temporary sector unprotect mode
44 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 15. temporary sector group unprotect waveforms table 7. temporary sector group unprotect parameter std. description test setup all speed options unit tvidr vid rise and fall time (see note) min 500 ns trsp reset# setup time for temporary sector unprotect min 4 us note: not 100% tested reset# ce# we# ry/by# tvidr 12v 0 or 3v vil or vih trsp tvidr program or erase command sequence
45 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 16. temporary sector group unprotect flowchart start reset# = vid (note 1) perform erase or program operation reset# = vih temporary sector unprotect completed(note 2) operation completed 2. all previously protected sectors are protected again. notes : 1. all protected sectors are temporary unprotected. vid=11.5v~12.5v. (if wp#/acc=vil, outermost boot sectors will remain protected)
46 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 17. silicon id read timing waveform tacc tce tacc toe toh toh tdf data out c2h a7h (top boot) a8h (bottom boot) vid vih vil add a9 add ce# a1 oe# we# add a0 data out data q0-q7 vcc 3v vih vil vih vil vih vil vih vil vih vil vih vil vih vil
47 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b write operation status figure 18. data# polling timing waveforms (during automatic algorithms) note: va=valid address. figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle . tdf tce tch toe toeh tacc trc toh address ce# oe# we# q7 q0-q6 ry/by# tbusy status data status data status data complement true valid data va va high z high z valid data tr u e
48 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 19. data# polling algorithm start read q7~q0 add. = va (1) ye s ye s ye s no no no q7 = data ? q7 = data ? q5 = 1 ? read q7~q0 add. = va pass fail (2) notes: 1. va=valid address for programming or erasure. 2. q7 should be rechecked even q5="1" because q7 may change simultaneously with q5.
49 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 20. toggle bit timing waveforms (during automatic algorithms) note: va=valid address; not required for q6. figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. tdf tce tch toe toeh tacc trc toh address ce# oe# we# q6/q2 ry/by# tbusy valid status (first read) valid status (second read) (stops toggling) valid data va va va va valid data
50 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b start read q7~q0 read q7~q0 yes no toggle bit q6 =toggle? q5=1? yes no (note 1) read q7~q0 twice (note 1,2) toggle bit q6= toggle? program/erase operation not complete, write reset command yes program/erase operation complete figure 21. toggle bit algorithm notes: 1. read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as q5 changes to "1".
51 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 22. q6 versus q2 note: the system can use oe# or ce# to toggle q2/q6, q2 toggles only when read at an address within an erase-suspended we# enter embedded erasing erase suspend enter erase suspend program erase suspend program erase suspend read erase suspend read erase erase resume erase complete erase q6 q2
52 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b figure 23. byte# timing waveform for read operations (byte# switching from byte mode to word mode) ac characteristics word/byte configuration (byte#) parameter description speed options unit jedec std -70 -90 telfl/telfh ce# to byte# switching low or high max 5 ns tflqz byte# switching low to output high z max 25 30 ns tfhqv b yte# switching high to output active min 70 90 ns tfhqv telfh dout (q0-q7) dout (q0-q14) va dout (q15) ce# oe# byte# q0~q14 q15/a-1
53 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b recommended operating conditions at device power-up ac timing illustrated in figure a is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a. ac timing at device power-up notes : 1. sampled, not 100% tested. 2. this specification is applied for not only the device power-up but also the normal operations. symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v tr input signal rise time 1,2 20 us/v tf input signal fall time 1,2 20 us/v vcc address ce# we# oe# data tvr tacc tr or tf tce tf vcc(min) gnd vih vil vih vil vih vil vih vil voh high z vol wp#/acc vih vil valid ouput valid address tr or tf tr toe tf tr
54 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b min. max. input voltage with respect to gnd on all pins except i/o pins -1.0v 12.5v input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v vcc current -100ma +100ma includes all pins except vcc. test conditions: vcc = 3.0v, one pin at a time. limits parameter min. typ.(2) max. units sector erase time 0.9 15 sec chip erase time 35 50 sec byte programming time 9 300 us word program time 11 360 us chip programming time byte mode 36 108 sec word mode 24 72 sec accelerated byte/word program time 7 210 us erase/program cycles 100,000 cycles latch-up characteristics erase and programming performance(1) note: 1.not 100% tested, excludes external system level over head. 2.typical values measured at 25 c,3.3v. parameter symbol parameter description test set typ max unit cin input capacitance vin=0 6 7.5 pf cout output capacitance vout=0 8.5 12 pf cin2 control pin capacitance vin=0 7.5 9 pf tsop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions ta=25 c, f=1.0mhz
55 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b part no. access operating standby package remark time (ns) current max. (ma) current max. (ua) kh29lv320cttc-70 70 30 5 48 pin tsop (normal type) KH29LV320CBtc-70 70 30 5 48 pin tsop (normal type) kh29lv320cttc-90 90 30 5 48 pin tsop (normal type) KH29LV320CBtc-90 90 30 5 48 pin tsop (normal type) kh29lv320cttc-70g 70 30 5 48 pin tsop pb free (normal type) KH29LV320CBtc-70g 70 30 5 48 pin tsop pb free (normal type) kh29lv320cttc-90g 90 30 5 48 pin tsop pb free (normal type) KH29LV320CBtc-90g 90 30 5 48 pin tsop pb free (normal type) ordering information
56 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b part name description kh 29 lv 70 c t t c g option: g: lead-free package blank: normal speed: 70: 70ns 90: 90ns temperature range: c: commercial (0?c to 70?c) package: t: tsop boot block type: t: top boot b: bottom boot revision: c density & mode: 320: 32mb, x8/x16 boot block type: lv: 3 v device: 29:flash 320
57 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b package information
58 p/n:pm1251 rev. 1.1, dec. 09, 2005 kh29lv320c t/b revision history revision no. description page date 1.1 1. modified content error p33,53 dec/09/2005
m acronix i nternational c o., l td . headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office : tel:+32-2-456-8020 fax:+32-2-456-8021 hong kong office : tel:+86-755-834-335-79 fax:+86-755-834-380-78 japan office : kawasaki office : tel:+81-44-246-9100 fax:+81-44-246-9105 osaka office : tel:+81-6-4807-5460 fax:+81-6-4807-5461 singapore office : tel:+65-6346-5505 fax:+65-6348-8096 taipei office : tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-262-8887 fax:+1-408-262-8810 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice. kh29lv320c t/b

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